1. Field of the Invention
The present invention is directed to an integrated circuit, particularly an integrated MOS circuit with low threshold voltage differences of the transistors therein, and to a manufacturing process for making such an integrated circuit.
2. Description of the Prior Art
In integrated MOS circuits with small transistor lengths, for example under 0.5 xcexcm, a phenomenon known as the xe2x80x9creverse short channel effectxe2x80x9d occurs. This effect is manifested as an increase of the cutoff voltage or threshold voltage given reduction of the channel length. An accumulation of dopant at the channel edges close to the source/drain regions is responsible for this effect. This accumulation of dopant is mainly caused by source/drain implantation damage at the channel edge. This cutoff voltage can increase by more than 100 mV in a transistor with a length of less than 0.5xcexc compared to a 10xcexc long transistor. This can be very disturbing, particularly for analog circuit design in which different transistor lengths occur in this range.
In current CMOS processes, an attempt is made to reduce by reducing the source/drain implantation damage by a technique known as RTP (Rapid Thermal Process). Rapid Thermal Process is a tempering range of 800xc2x0 C. through 1000xc2x0 C. for a time duration of 5 through 10 seconds.
The source/drain implantation damage, however, can only be incompletely achieved using this technique, which has the disadvantage that the entire thermal exposure in the CMOC process is thereby increased, and the source/drain profiles and channel profiles can be widened by the additional thermal load.
An IEEE paper at the IEDM 95, 34.4.1 through 34.4.4, pages 859 through 862 discloses nitrogen implantation into a gate oxide close to edge coverings (spacers), causing the resistance of parasitic resistors produced in the transistor due to a local reduction of the dopant concentration, to increase.
An object of the present invention is to provide an integrated MOS circuit and an appertaining manufacturing process, wherein transistors with different lengths have the same cutoff voltage insofar as possible, without an additional thermal load in the manufacturing process.
The above object is achieved in accordance with the principles of the present invention in an integrated circuit having at least two MOS field effect transistors, each having a drain region, a source region and a channel region, with the respective channel regions of the two transistors being of different unequal lengths, and wherein in each field effect transistor the source region and the drain region extend a length into the channel region, and contain regions doped with nitrogen that extend further into the channel region than the remainder of the source region and the drain region.
The above object is also achieved in a method for manufacturing an integrated circuit having at least two MOS field effect transistors, each transistor having a semiconductor body in which a source region, a drain region and channel region are generated, the respective channel regions of the two transistors being of different lengths, and wherein nitrogen is implanted into the semiconductor body at an angle differing from 90xc2x0, at the opposite edges of each of the channel areas, prior to the generation of a covering over the channel and prior to a last doping for generating the source region and the drain region.
In an embodiment of the inventive method, the dopant concentration and the angle are selected so that an area of the source region and the drain region in each transistor, generated by a first doping prior to the nitrogen implantation, is substantially enveloped by a doped area generated by the nitrogen implantation into the semiconductor body, this area doped with nitrogen proceeding further into the channel region than the doped area generated prior to the nitrogen implantation.
In a further embodiment, the angle of nitrogen implantation is less than or equal to 30xc2x0.